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| data sheet NL10276AC24-05 tft color lcd module document no. en0208ej2v0ds00 date published april 1997 m printed in japan 1996 description NL10276AC24-05 is a tft (thin film transistor) active matrix color liquid crystal display (lcd) comprising amorphous silicon tft attached to each signal electrode, a driving circuit and a backlight. NL10276AC24-05 has a built-in backlight/inverter. the 31cm diagonal display area contains 1024 768 pixels and can display full-color (more than 16 million colors) simultaneously by analog rgb signals of xga, svga, vga, vga-text, pc-9801, ntsc, and pal. NL10276AC24-05 is a succeeding model for nl10276ac24-02, and it has two additional operating modes of ntsc and pal. features a analog rgb interface a vertical screen expansion (multi-scan)~xga, svga, vga, vga-text, pc-9801, ntsc, pal. a high luminous / low reflection a incorporated edge-light type backlight with inverter. applications a engineering workstation (ews), personal computer (pc), word processor a display terminals for control system a new media a monitors for process controller 31cm (12.1 type), 1024 768 pixels, full color vertical screen expansion (multi-scan), incorporated backlight with inverter the information in this document is subject to change without notice.
2 NL10276AC24-05 structure and functions a tft color lcd module comprises a tft lcd panel, lsis for driving liquid crystal, and a backlight. the tft lcd panel is composed of a tft array glass substrate superimposed on a color filter glass substrate with liquid crystal filled in the narrow gap between two substrates. the backlight apparatus is located on the backside of the lcd panel. rgb (red, green, blue) data signals are sent to lcd panel drivers after modulation into suitable forms for active matrix addressing through signal processor. each of the liquid crystal cells acts as an electro-optical switch that controls the light transmission from the backlight by a signal applied to a signal electrode through the tft switch. block diagram i/f aif r g b vsync hsync clk lcd timing controller de desel clamp cpsel field analog h-driver cntdat cntclk cntstb cntsel tft-lcd panel h:1024 3 (r, g, b) v:768 inverter v ddb gndb * brtc brth brtl aca 768 lines analog h-driver 1536 lines 1536 lines dc / dc converter on off v cc v dd gnd powc lcd module amp backlight v - driver * 1 : gndb is connected to the module frame ground. 3 NL10276AC24-05 outline of characteristics (at room temperature) display area 245.76 (h) 184.32 (v)mm drive system a-si tft active matrix display colors full-color number of pixels 1024 768 pixel arrangement rgb vertical stripe pixel pitch 0.24 (h) 0.24 (v)mm module size 290 (h) 225.0 (v) 17.0 max. (d)mm weight 970 g (typ.) contrast ratio 150:1 (typ.) viewing angle (more than the contrast ratio of 10:1) ? horizontal: 50? (typ. left side, right side) ? vertical : 20? (typ. upper side), 20? (typ. lower side) designed viewing direction ? wider viewing angle with contrast ratio : down side (6 o'clock) ? wider viewing angle without image reversal : up side (12 o'clock) ? optimum grayscale ( g = 2.2) : perpendicular color gamut 40% (min., at center, to ntsc) response time 40 ms (max.), "white" to "black" luminance 200 cd/m 2 (typ.) signal system analog rgb signals, synchronous signals (hsync, vsync), dot clock supply voltage 3.3 v, 12 v, 12 v backlight edge light type, two cold cathode fluorescent lamps with inverter power consumption 14.4 w (typ.) 4 NL10276AC24-05 item specifications unit module size 290.0 0.5(h) 225.0 0.5(v) 17.0 max. (d) mm display area 245.76(h) 184.32 (v) mm number of pixels 1024(h) 768 (v) pixel dot pitch 0.08(h) 0.24 (v) mm pixel pitch 0.24(h) 0.24 (v) mm pixel arrangement rgb(red, green, blue) vertical stripe C display colors full-color color weight 1000 (max.) g general specifications note : a variable resistor for the luminance control is extra. absolute maximum ratings parameter symbol ratings unit remarks v cc C0.3 to +4.6 v supply voltage v dd C0.3 to +14 v v ddb C0.3 to +14 v logic input voltage vin1 C0.3 to +5.5 v r, g, b input voltage vin2 C4.0 to +4.0 v clk input voltage vin3 C7.0 to +7.0 v storage temp. tst C20 to +60 ? c C operating temp. top 0 to +50 ? c module surface * humidity 95% relative humidity ta = 40?c 85% relative humidity 40?c 5 NL10276AC24-05 parameter symbol min. typ. max. unit remarks v cc 3.0 3.3 3.6 v for logic supply voltage v dd 11.4 12.0 12.6 v for lcd driving v ddb 11.4 12.0 12.6 v for backlight logic input "l" voltage v il 0 C 0.8 v logic input "h" voltage v ih 2.2 C 5.25 v logic input "l" current 1 i il1 C1080 C C m a logic input "h" current 1 i ih1 CC10 m a logic input "l" current 2 i il2 C670 C C m a logic input "h" current 2 i ih2 CC80 m a logic input "l" current 3 i il3 C90 C C m a logic input "h" current 3 i ih3 CC0 m a logic input "l" current 4 i il4 C10 C C m a logic input "h" current 4 i ih4 C C 130 m a clk input voltage v iclk 0.4 C 1.0 vp-p clk dc input level v idc -clk C4.5 C +4.5 v supply current i ddb C 710 800 ma v ddb = 12 v i dd C 480 700 ma v dd = 12 v i cc C 120 200 ma v cc = 3.3 v electrical characteristics (1) logic/lcd driving/backlight ta = 25?c ttl level vcc=3.3 v for cntsel, cpsel and powc terminals for brtc terminal for aca terminal except the above logic input terminals for clk 1 000 pf 510 w clk clk input equivalent circuit (2) input video signals (r, g, b) ta = 25?c parameter symbol min. typ. max. unit remarks video input voltages v irgb 0 C 0.7 vp-p video input limits v idc -rgb C2.5 C +2.5 v for rgb zi = 75 w * 1 : ta = 0 to 50?c : v iclk = 0.6 v p-p (min.). ta = 25?c : v iclk = 0.4 v p-p (min.). * 2 : dot-checkered pattern * 1 * 2 * 2 * 2 (black) (white) 6 NL10276AC24-05 supply voltage sequence voltage v ddb powc v dd v cc time logic signals (synchronous signals, control signals) 0< 0< 0< 0< caution wrong power sequence may damage to the module. (1) logic signals (synchronous signals and control signals) should be "0" voltage (v), when v cc is not input. if higher than 0.3 v is input to signal lines, the internal circuit will be damaged. (2) lcd module will shut down the power supply of driving voltage to lcd panel internally, when one of clk, hsync, vsync, de (at de mode) is not input more than 90 ms typically. during this period, the display data are unstable. but the backlight works correctly even this period, and the backlight can be controlled by brtc signal. (3) the on/off switching of backlight should operate while logic signals are supplied. if the backlight power supply (v ddb ) is turned on / off without logic signals, unstable data will be displayed. (4) keep powc signal "l" more than 200 ms after the power supply (v cc ) is input, if powc signal is controlled. (refer to pin function) (5) analog rgb inputs are independent from this power supply sequence. (6) it is better for the timing between logic signals and v cc as follows. v cc logic signals 0 8 NL10276AC24-05 pin no. symbol pin no. symbol 1 gnd 8 clamp 2 cntsel 9 gnd 3 cntdat 10 field 4 cntstb 11 gnd 5 gnd 12 n.c. 6 cntclk 13 gnd 7 cpsel note : n.c. (no connection) should be open. (4) connector 4 cn4 : il-z-13pl1-smty adaptable socket : il-z-13s-s125c3 supplier : japan aviation electronics industry limited (jae) ? ? 9 NL10276AC24-05 symbol logic description clk positive dot clock input, timing signal for display data hsync negative horizontal synchronous signal input (ttl level) vsync negative vertical synchronous signal input (ttl level) de positive data enable signal input (ttl level) back-porch becomes free, when desel is "h". back-porch becomes fix, when desel is "l". (de should be fixed "h" or "l".) r C red video signal input (0.7 vp-p, 75 w ) g C green video signal input (0.7 vp-p, 75 w ) b C blue video signal input (0.7 vp-p, 75 w ) clamp C clamp timing signal of black level (ttl level) valid for only cpsel is "l". cntsel C display control signal in case of serial communication. (ttl level) h or open : default l : external control cntdat positive display control data (serial data) (ttl level) cntclk positive clk for display control data (ttl level) cntstb positive latch pulse for display control data (ttl level) desel positive de function select signal (ttl level) h : de mode l or open : fixed mode cpsel C clamp signal function select signal (ttl level) h or open : default l : clamp signal is possible field C field select signal (valid for only ntsc/pal-mode) (ttl level) 1st field is "h". 2nd field is "l". field terminal is possible to use "open" in case of except ntsc/ pal-mode. powc positive power control signal (ttl level) h or open : logic, lcd power is on l : logic, lcd power is off (*1) brth/brtl C pins for backlight brightness control connect 10 kw variable resistor (*2) or voltage control (*3). brtc positive backlight on/off control signal h or open : backlight on l : backlight off aca positive luminance control signal h or open : normal luminance l : low luminance (1/2 of normal luminance) v cc Cv cc (+3.3 v) power supply for logic v dd Cv dd (+12 v 5%) power supply for lcd v ddb Cv ddb (+12 v 5%) power supply for backlight gndb ground for backlight (v ddb ) gndb is connected to the module frame ground. gnd C signal ground for logic / lcd driving (v cc , v dd ) (connect to a system ground.) pin function 10 NL10276AC24-05 *1 : when powc is "l" logic input signal should be all "0 v". if input signals are more than "0.3 v", inside circuits of the lcd module may be broken. when powc is "l", serial communication data is clear. please set it again. *2 : the variable resistor for brightness control should be 10 k w type, and zero point of the resistor corre- sponds to the minimum of luminance. *3 : in case of voltage control for brightness by brth/brtl, at first, set brth to be "0 v". and brtl input voltage can control the brightness. when brtl input voltage is "1 v" the luminance become maximum. and when its voltage is "0 v", the luminance becomes minimum. brth brtl (10 k w 5% , b curve) < connection of the variable resistor to pins > functions (1) serial data this lcd module has following functions by serial data input (table 1). no. functions detail 1 expansion mode see table 2 (screen mode) and expansion function 2 display position control (horizontal) see table 6 3 display position control (vertical) see table 3 4 clk delay control see table 4 5 hsync period count number see table 7 6 clk fall/rise synchronous change see table 5 7 input frequency selection see table 8 how to use the above functions if cntsel is "l", the above functions are valid. (cntsel is "h" or open, default values are valid.) after serial data are transferred, the data is latched by cntstb. once, the data is latched, the above functions are effective. please keep cntstb to be "l" during transferring data. input data can be changed during power on, but lcd display may be disturbed. when the serial data are changed, we recommend that the backlight power is off using brtc function. attention input data can be changed during power on, but lcd display may be disturbed. when the serial data are changed, we recommend that the backlight power is off using brtc function. 11 NL10276AC24-05 cntdat cntstb cntclk d0 d1 d3 d2 d41 d42 d43 d44 (2) serial communication timing and waveform parameter symbol min. max. unit remarks clk pulse width twck 50 C ns cntclk clk frequency fclk C 5 mhz data setup-time tdst 50 C ns cntdat data hold-time tdhl 50 C ns latch-pulse width twlp 50 C ns cntstb latch setup-time tlst 50 C ns rise / fall time tr, tf C 50 ns cnt v cc v cc cntdata 50% gnd tdst tdhl twck 90% cntclk 50% 50% 10% gnd tr tf tlst twlp v cc cntstb gnd 12 NL10276AC24-05 data data name function d0 vex3 expansion mode see table 2 d1 vex2 expansion mode d2 vex1 expansion mode d3 vex0 expansion mode d4 vd10 vertical display position (msb) see table 3 d5 vd9 vertical display position d6 vd8 vertical display position d7 vd7 vertical display position d8 vd6 vertical display position d9 vd5 vertical display position d10 vd4 vertical display position d11 vd3 vertical display position d12 vd2 vertical display position d13 vd1 vertical display position d14 vd0 vertical display position (lsb) d15 delay6 clk delay (msb) see table 4 d16 delay5 clk delay d17 delay4 clk delay d18 delay3 clk delay d19 delay2 clk delay d20 delay1 clk delay d21 delay0 clk delay (lsb) d22 cks clk reverse signal see table 5 d23 hd8 horizontal display position (msb) see table 6 d24 hd7 horizontal display position d25 hd6 horizontal display position d26 hd5 horizontal display position d27 hd4 horizontal display position d28 hd3 horizontal display position d29 hd2 horizontal display position d30 hd1 horizontal display position d31 hd0 horizontal display position (lsb) d32 hse10 horizontal count number (msb) see table 7 d33 hse9 horizontal count number d34 hse8 horizontal count number d35 hse7 horizontal count number d36 hse6 horizontal count number d37 hse5 horizontal count number d38 hse4 horizontal count number d39 hse3 horizontal count number d40 hse2 horizontal count number d41 hse1 horizontal count number d42 hse0 horizontal count number (lsb) d43 mod1 clk frequency select see table 8 d44 mod0 clk frequency select table 1. cntdat composition msb : most significant bit lsb : least significant bit 13 NL10276AC24-05 table 2. display mode (vex3 to vex0 ; 4 bit) vex3 vex2 vex1 vex0 vertical magnification display mode display image 0000 1 xga standard (note 1) 0001 1.25 svga 0010 1.6 pc98, vga, text 0011 C prohibit see display image 0101 2.5 pal 0110 3.2 ntsc 0111 C prohibit 1 x x x C prohibit note 1 : display mode is xga, when cntsel is "h" or "open". vd10 vd9 vd8 vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 vertical position [h] (note 2) 00000000000 prohibit 00000000001 prohibit 00000000010 prohibit 00000000011 prohibit 00000000100 4 00000000101 5 ??????????? ? ??????????? ? ??????????? ? 11111111101 2045 11111111110 2046 11111111111 2047 (note 3) table 3. vertical position (vd10 to vd0 ; 11 bit) note 2 : this is horizontal line number for effecting video signal from vsync-fall. note 3 : the maximum vertical position is vsync total. note 4 : vertical position is fixed at 35 h, when cntsel is "h" or "open". 14 NL10276AC24-05 table 4. clock (clk) delay (delay6 to delay0 ; 7 bit) da (6 : 0) delay ( note 5 ) value 00h 7.0 ns 01h 7.6 ns 02h 8.2 ns 03h 8.8 ns 04h 9.4 ns 05h 10.0 ns 06h 10.5 ns 07h 11.2 ns 08h 11.8 ns 09h 12.4 ns 0ah 13.0 ns 0bh 13.7 ns 0ch 14.2 ns 0dh 14.8 ns 0eh 15.3 ns 0fh 15.9 ns 10h 16.6 ns 11h 17.2 ns 12h 17.8 ns 13h 18.4 ns 14h 18.9 ns 15h 19.5 ns 16h 20.1 ns 17h 20.7 ns 18h 21.4 ns 19h 22.0 ns 1ah 22.6 ns 1bh 23.2 ns 1ch 23.8 ns 1dh 24.4 ns 1eh 24.9 ns 1fh 25.6 ns 20h 26.3 ns 21h 26.9 ns 22h 27.4 ns 23h 28.1 ns 24h 28.5 ns 25h 29.1 ns 26h 29.7 ns 27h 30.3 ns 28h 31.0 ns 29h 31.6 ns 2ah 32.2 ns 2bh 32.8 ns da (6 : 0) delay ( note 5 ) value 2ch 33.3 ns 2dh 33.9 ns 2eh 34.4 ns 2fh 35.1 ns 30h 35.6 ns 31h 36.2 ns 32h 36.8 ns 33h 37.5 ns 34h 37.9 ns 35h 38.5 ns 36h 39.1 ns 37h 39.7 ns 38h 40.4 ns 39h 41.0 ns 3ah 41.5 ns 3bh 42.1 ns 3ch 42.6 ns 3dh 43.2 ns 3eh 43.8 ns 3fh 44.4 ns 40h 45.0 ns 41h 45.6 ns 42h 46.2 ns 43h 46.8 ns 44h 47.3 ns 45h 47.8 ns 46h 48.4 ns 47h 49.0 ns 48h 49.6 ns 49h 50.2 ns 4ah 50.8 ns 4bh 51.4 ns 4ch 51.9 ns 4dh 52.6 ns 4eh 53.1 ns 4fh 53.7 ns 50h 54.5 ns 51h 55.0 ns 52h 55.6 ns 53h 56.3 ns 54h 56.8 ns 55h 57.4 ns 56h 57.9 ns 57h 58.5 ns da (6:0) delay ( note 5 ) value 58h 59.2 ns 59h 59.8 ns 5ah 60.4 ns 5bh 61.1 ns 5ch 61.6 ns 5dh 62.2 ns 5eh 62.7 ns 5fh 63.3 ns 60h 64.0 ns 61h 64.7 ns 62h 65.3 ns 63h 66.0 ns 64h 66.5 ns 65h 67.1 ns 66h 67.7 ns 67h 68.3 ns 68h 68.9 ns 69h 69.5 ns 6ah 70.1 ns 6bh 70.7 ns 6ch 71.2 ns 6dh 71.9 ns 6eh 72.4 ns 6fh 73.1 ns 70h 73.6 ns 71h 74.2 ns 72h 74.8 ns 73h 75.4 ns 74h 75.9 ns 75h 76.5 ns 76h 77.0 ns 77h 77.7 ns 78h 78.3 ns 79h 79.0 ns 7ah 79.6 ns 7bh 80.2 ns 7ch 80.8 ns 7dh 81.4 ns 7eh 81.9 ns 7fh 82.5 ns note 5 : da (6:0) means delay 6 (d15) to 0 (d21) 15 NL10276AC24-05 mod1 mod0 upper limit of vd6 to vd0 clk-delay setting (hexadecimal) 0 0 prohibit 0 1 59h 1 0 6bh 1 1 7fh note 8 : this delay value is typical at ta = 25?c, v cc = 3.3 v. by changing ambient temperature and power supply, the delay will be changed also. see the following references. q variation of clk delay by temperature drift. (as reference) the temperature constant of clk delay is 0.2 % / ?c. calculated example: in case that delay time is 20 ns at ta = 25?c; (a) in case of ta rising to 50 ?c. increase of delay time ? (50?c-25?c) 0.002 20 ns = +1 ns so, the total delay time is 21 ns at ta = 50?c. (b) in case of ta falling to 0?c. decrease of delay time ? (0?c-25?c) 0.002 20ns = C1 ns so, the total delay time is 19 ns at ta = 0?c. w variation of clk delay time against v cc voltage change. (as reference) increase of 35 % / v in case of rising from v cc = 3.3 v. decrease of 48 % / v in case of falling from v cc = 3.3 v. calculated example: in case that delay time is 20 ns at v cc = 3.3 v. (a) in case of v cc rising to 3.6 v. decrease of delay time ? (3.3 v-3.6 v) 0.35 20 ns = C2.1 ns so, the total delay time is 17.9 ns at v cc = 3.6 v. (b) in case of v cc falling to 3.0 v. increase of delay time ? (3.3 v-3.0 v) 0.48 20 ns = +2.88 ns so, the total delay time is 22.88 ns at v cc = 3.0 v. table 5. clk reverse signal cks function data is sampled on rising edge of clk. data is sampled on falling edge of clk. note 9 : cks is "0", when cntsel is "h" or "open". 0 1 16 NL10276AC24-05 table 6. display horizontal position (hd8 to hd0; 9 bit) hd8 hd7 hd6 hd5 hd4 hd3 hd2 hd1 hd0 horizontal position [clk] ( note 10 ) 000000000 prohibit 000000001 prohibit ???????? ? ? ????????? ? 000111111 prohibit 001000000 64 001000001 65 ????????? ? ????????? ? 111111101 509 111111110 510 111111111 511 note 10 : this is clk number from hsync-fall to effecting video signal. note 11 : horizontal position is set at 296 clk, when cntset is "h" or "open". hse10 hse9 hse8 hse7 hse6 hse5 hse4 hse3 hse2 hse1 hse0 clk number ( note 12 ) 00000000000 0 00000000001 1 00000000010 2 00000000011 3 00000000100 4 ??????????? ? ??????????? ? ??????????? ? 11111111101 2045 11111111110 2046 11111111111 2047 table 7. display horizontal clk numbers (hse10 to hse0; 11 bit) note 12 : this is from one falling edge of hsync to the next hsync. note 13 : clk number is set 1344 clk, when cntsel is "h" or "open". note 14 : set hse0 to 10 complying with clk number of hsync. if the setting value is different from actual input signal, it cause a malfunction. table 8. setting of clk frequency (mod1 to mod0; 2 bit) mod1 mod0 clk frequency [mhz] 0 0 prohibit 0 1 65 to 79 1 0 50 to 65 1 1 20 to 50 note 15 : set mod0 and mod1 complying with input clk frequency. note 16 : clk frequency is set 65 to 79 mhz, when cntsel is "h" or "open". 17 NL10276AC24-05 expansion function how to use expansion function and screen image expansion mode is a function to expand screen. for example, vga signal has 640 480 pixels. but, if the display data can expanded to 1.6 times vertically and horizontally, vga screen image can be displayed fully on the screen of xga resolution. this lcd module has the function of expanding vertical direction as shown in table 1. and expanding horizontal direction is possible by setting input clk frequency which is equivalent to the magnification. it is necessary to make this clk outside of this lcd module. display image of after two pages is display example, when de function is default and hd and vd are set to most suitable frequency. and when de function is used, hd and vd become default. please adjust the display to the best position by de signal. please adopt these modes after evaluating display quality, because of becoming bad display in some cases. magnification vertical horizontal * xga 1024 768 1 1 svga 800 600 1.25 1.25 vga 640 480 1.6 1.6 vga text 720 400 1.6 1.4 pc-9801 640 400 1.6 1.6 ntsc 640 (vertical 240 2) 3.2 1.6 pal 640 (vertical 280 2) 2.5 1.6 input display resolution the followings show display magnifications for each mode. * the horizontal magnification multiples the input clock (clk). input clk = system clk horizontal magnification example : in case of xga, vga and pc-9801, clk frequency can be decided as follows. xga : (system clk (65mhz)) 1.0=65mhz vga : (system clk (25.175mhz)) 1.6=40.28mhz pc-9801 : (system clk (21.053mhz)) 1.6=33.68mhz 18 NL10276AC24-05 setting serial data for expansion input signal mode clk hsync vsync horizontal vertical count dsp count dsp hse hd vd number ( note 1 ) number ( note 1 ) [mhz] [khz] [hz] [clk] [clk] [h] [h] (a) (b) C (c) calculation formula (a) (b) = (c) vertical magnitude horizontal magnitude xga 65.000 48.363 60.004 1344 296 806 35 (a) 1 (b) 1 = (c) 75.000 56.476 70.069 1328 280 806 35 79.000 58.088 72.980 1360 328 807 39 78.750 60.023 75.029 1312 272 800 31 svga 36.000 35.156 56.25 1024 200 625 24 (a) 1.25 (b) 1.25 40.000 37.879 60.317 1056 216 628 27 50.000 48.077 72.188 1040 184 666 29 49.500 46.875 75.000 1056 240 666 24 vga 25.175 31.469 59.940 800 144 525 35 (a) 1.6 (b) 1.6 31.500 37.861 72.809 832 168 520 31 31.500 37.500 75.000 840 184 500 19 31.334 34.971 66.611 896 176 525 6 vga 28.322 31.469 70.087 900 153 449 37 (a) 1.4 (b) 1.4 text 31.500 37.927 85.040 936 180 446 45 pc-9801 21.053 24.827 56.424 848 144 440 33 (a) 1.6 (b) 1.6 433 25.175 31.469 70.086 800 144 449 37 ntsc 20.000 15.734 59.940 C 205 262.5 9 1271 = (b) = (c) pal 20.000 15.625 50.000 C 205 312.5 9 1280 = (b) = (c) module serial-data setting note 1 : dsp = display start period. dsp is the total of "pulse-width" and "back-porch". note 2 : hd and vd are approximate values. set hd and vd in case of adjusting display to the screen center. note 3 : the pulse-width of hsync, vsync and back-porch are the same as xga-mode. (standard-mode). note 4 : detail of hse is mentioned in clk number of table 7. note 5 : detail of hd is mentioned in horizontal position of table 6. note 6 : detail of vd is mentioned in vertical position of table 3. 19 NL10276AC24-05 display image (1) svga mode (800 600) (2) vga mode (640 480) (3) pc-9801 mode (640 400) (4) vga-text mode (720 400) (5) ntsc mode (640 240) (6) pal mode (640 280) xga (1024 768 pixels) black display area valid area horizontal : 1.25 (1000 pixels) vertical : 1.25 (750 pixels) horizontal : 1.6 (1024 pixels) vertical : 1.6 (768 pixels) horizontal : 1.6 (1024 pixels) vertical : 1.6 (640 pixels) horizontal : 1.4 (1008 pixels) vertical : 1.6 (640 pixels) horizontal : 1.6 (1024 pixels) vertical : 3.2 (768 pixels) horizontal : 1.6 (1024 pixels) vertical : 2.5 (700 pixels) 20 NL10276AC24-05 input signal timing (1) xga-mode (standard) without use serial communication (cntsel = "h" or open) name symbol min. typ. max. unit remarks clk frequency 1 / tc 52.0 65.0 79.0 mhz xga standard C 15.385 C ns rise / fall tcrf C C 10.0 ns C duty tch / tc 0.4 0.5 0.6 C C hsync period th 16.6 20.677 22.7 m s 48.363 khz C 1344 C clk (typ.) display thd C 15.754 C m sC C 1024 C clk front-porch thf C 0.369 - m sC 10 24 - clk pulse-width thp C 2.092 C m sC 16 136 C clk back-porch thb 1.0 2.462 C m sC 44 160 C clk pulse-width thpb 1.8 C C m sC + back-porch thch 4.0 C C ns C thcs 2.0 C C ns C thvh 4.0 C C ns C thvs 1.0 C C clk C rise / fall thrf C C 10.0 ns C vsync period tv 13.3 16.665 18.5 ms 60.004 hz C 806 C h (typ.) display tvd C 15.880 C ms C C 768 C h front-porch tvf C 62.031 C m sC 13Ch pulse-width tvp C 124.06 C m sC 26Ch back-porch tvb C 599.63 C m sC 529Ch rise / fall tvrf C C 10.0 ns ntsc/pal mode field timing tfi 1C Ch C de setup time tds 2.0 C C ns C hold time tdh 4.0 C C ns C rise/fall tdrf C C 10.0 ns C analog rgb clk-hsync timing hold / setup time v-hsync timing hold / setup time tda 5.0 C C ns C 21 NL10276AC24-05 without use serial communication (cntsel = "h" or open) * v ih = 2.2 v (min.) to 5.25 v (max.) v il = 0 v (min.) to 0.8 v (max.) clk r g b de hsync vsync hsync tc tch v idcclk v iclk gnd v ih * 1.5 v v il * v ih * 1.5 v v il * v ih * 1.5 v v il * v ih * 1.5 v v il * v ih * 1.5 v v il * tcrf tds tdh tdrf tda thch thcs thrf tvrf thvh thvs 22 NL10276AC24-05 23 NL10276AC24-05 mod1 mod0 ta [clk] tb [clk] tc [ns] 0 0 prohibit 0 1 44 32 1 0 34 22 200 min. 1 1 28 18 (2) timing for generating clamp signal internally hsync display period clamp ta tb tc (3) timing for inputting clamp signal from outside hsync display period clamp ta tb tc note : exclude noises on analog rgb signal. because during clamp = " l", the pedestal level of analog rgb signals is sampled. if noises are on the analog signals, luminance level of display is changed and the display becomes bad. items min. typ. max. unit remarks ta 0.1 C C m sC tb 0.3 C C m sC tc 0.2 C C m sC note : exclude noises on analog rgb signal. because during clamp = "l", the pedestal level of analog rgb signals is sampled. if noises are on the analog signals, luminance level of display is changed and the display becomes bad. 24 NL10276AC24-05 tvp vsync hsync xga mode (cntsel="h" or "open") r g b r g b hsync xga mode (cntsel="h" or "open") clk invalid tvb 1 line invalid valid d (0, x) d (1, x) d (2, x) thp thb 1 clk d (x, 0) d (x, 1) d (x, 3) d (x, 2) d (x, 4) 0 1 2 296 297 012345 3536 input signal and display position (xga standard timing) (1) delsel="l" pixels d ( 0, 0 ) d ( 1, 0 ) d ( 2, 0 ) d ( 767, 0 ) d ( 0, 1 ) d ( 1, 1 ) d ( 767, 1 ) d ( 0, 2 ) d ( 767, 2 ) d ( 0, 1023 ) d ( 767, 1023 ) 25 NL10276AC24-05 (2) delsel="h" clk data de hsync de data vsync hsync data de invalid invalid tds tdh thpd invalid invalid valid invalid invalid valid tvp+tvb 26 NL10276AC24-05 general caution warning do not touch an inverter --on which is stuck a caution label-- while the lcd module is under the operation, because of dangerous high voltage. attention input data can be changed during power on, but lcd display may be disturbed. when the serial data are changed, we recommend that the backlight power is off using brtc function. (1) caution when taking out the module q pick the pouch only, when taking out module from a shipping package. (2) cautions for handling the module q as the electrostatic discharges may break the lcd module, handle the lcd module with care. peel a protection sheet off from the lcd panel surface as slowly as possible. w as the lcd panel and back-light element are made from fragile glass material, impulse and pressure to the lcd module should be avoided. e as the surface of polarizer is very soft and easily scratched, use a soft dry cloth without chemicals for cleaning. r do not pull the interface connectors in or out while the lcd module is operating. t put the module display side down on a flat horizontal plane. y handle connectors and cables with care. u the torque to mounting screws should be less than 0.392n ? m (4 kgf ? cm). (3) cautions for the operation q when the module is operating, do not lose clk, hsync, or vsync signals. if any one of these signals is lost, the lcd panel would be damaged. w obey the supply voltage sequence. if wrong sequence is applied, the module would be damaged. e connect the variable resistor or fixed resistor (10 k w or less) to the pin of brth and brtl. if the resistors are not connected, the life of fluorescent lamp would be short. r please use a range of electrical characteristics. if use over range of absolute maximum rating, we can not guarantee the operation of lcd. (4) cautions for the atmosphere q dew drop atmosphere should be avoided. w do not store and / or operate the lcd module in a high temperature and/or humidity atmosphere. storage in an electro-conductive polymer packing pouch and under relatively low temperature atmos- phere is recommended. (5) cautions for the module characteristics q do not apply fixed pattern data signal to the lcd module at product aging. applying fixed pattern for a long time may cause image sticking. (6) other cautions q do not disassemble and / or reassemble lcd module. w do not re-adjust variable resistor or switch etc. e when returning the module for repair or etc., please pack the module not to be broken. we recommend to use the original shipping packages. 27 NL10276AC24-05 liquid crystal display has following specific characteristics. these are not defects or malfunction. the display condition of lcd module may be affected by the ambient temperature. the lcd module uses cold cathode tube for backlight. the optical characteristics, like luminance or uniformity, will change during life time. uneven brightness and/or small spots may be noticed depending on different display patterns. 28 NL10276AC24-05 outline drawing : front view (unit in mm) c l 4- 3.5 (4) (5) 215 0.3 290 0.5 252.8 0.3 (bezel opening) (245.76) (active area) 280 0.3 (4) (4) (5) 280 0.3 (2.8) (2.4) max.17 (4) (5) (4) (5) (4) (5) (4) (5) 255 0.5 188.8 0.3 (bezel opening) (184.32) (active area) 215 0.3 (4) f note : the torque to mounting screws should be less than 0.392 n m (4 kgf cm). 29 NL10276AC24-05 outline drawing : rear view (unit in mm) 76 2402 k2000a the tft color lcd 121blm-3 nl 10276ac24-05 a100100100100 es2228421 made in japan b/l lot.no. note : the torque to mounting screws should be less than 0.392 n m (4 kgf cm). (55) (29) (73.5) 4-m3br (48.6) (82.3) (9.1) (210) (0.8) (3.2) (59.2) (6) (3) 30 NL10276AC24-05 31 NL10276AC24-05 no part of this document may be copied in any form or by any means without the prior written consent of nec corporation. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. NL10276AC24-05 |
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